In the coming decades, chipmakers will not be able to make faster silicon chips by integrating smaller transistors on a single chip because the silicon transistors are too small. Breaks easily and at the same time very expensive.
There are many challenges that need to be overcome if the materials people are studying are going to go beyond silicon. Now, UC Berkeley researchers have found a way to cross that hurdle: They've developed a reliable way to make fast, low-power nanoscale transistors using a compound semiconductor material . Their method is simpler, and certainly cheaper, than the current method.
Compared with silicon, compound semiconductors have better electrical properties, which means transistors made from them consume less energy and are faster. These materials, which are already present in expensive specialty applications, such as military communications equipment, will help refine more promising alternatives to silicon, such as graphite and carbon nanotubes.
But wafers made of compound semiconductor materials are also fragile and expensive, "only if you don't have to think about cost," says Ali Javey, associate professor of electrical engineering and computer science at UC Berkeley, for example, Compound semiconductors are marketed for expensive military communications chips.
The researchers believe they can overcome this vulnerability and high price by simply growing compound semiconductor transistors on a supporting silicon wafer, a method compatible with existing chip-making facilities.
However, compound semiconductors cannot be grown on silicon surfaces, and the mismatch between the crystal structures of the two materials makes this difficult to do well. However, the Berkeley research group has shown that transistors made of compound semiconductors can be grown on another surface and then transferred to silicon wafers. “This is a plausible approach, but the practical difficulty is that compound semiconductors are difficult to grow,” said Jesús del Alamo, a professor of electrical engineering and computer science at MIT who was not involved in the Wei's research work.
The technique demonstrated by the Berkeley researchers uses indium arsenide. They grew the material on a gallium antimonide wafer protected by a protective top layer made of aluminum gallium antimonide. The wafer can grow high-quality crystalline indium arsenide thin films, and the protective layer is then chemically etched to engrave nanometer-scale strips of indium arsenide. The researchers picked up the nanoribbons with a rubber stamp and placed them on a silicon wafer, which would provide structural support for the indium arsenide. The material is coated with silicon dioxide, which acts as an insulator for the transistor. To complete the transistor, the metal gates need to be lowered so that current can flow in and out.
Garvey's team described the performance of indium arsenide transistors made in this way in a paper published last week in the online journal Nature. These transistors, about 500 nanometers long, perform like compound semiconductor transistors, which are fabricated using more sophisticated techniques, Garvey said. The Berkeley research group's indium arsenide transistors are much faster than silicon transistors while consuming less power, requiring only 0.5 volts compared to 3.3 volts for silicon. And their transconductance (adaptability to voltage changes) is eight times that of comparable-sized silicon transistors. "Considering how these devices are made, this performance is very good," said Dmitri Antoniadis, a professor of electrical engineering at MIT.
Garvey points out that this process is used to make indium arsenide transistors, and a similar process is used to make a type of chip called "silicon-on-insulator (SOI)" electronics, which requires placing one silicon wafer on another It can only be produced on the wafer of the material. For this reason, he named them Insulating X (XOI: any material on an insulator).
The insulator X device made by this process, which is at the wafer level, is more complex than SOI because it requires the integration of several different types of materials, and the wafers used to make them come in different sizes, said Michael Mayberry, director of component research and development at Intel. ) said, "There are many forms, which means that this process can go wrong," he said. For the past three years, Intel has been working on ways to grow compound semiconductors, directly on silicon wafers, by growing a buffer layer between them. So far, they've had to use very thick buffer layers, which affected the transistor's performance, but Mayberry said they've shown that it works.
The value of Garvey's work, according to Mayberry, is that it shows that indium arsenide transistors perform well, and that's how they do when scaled down to the nanometer size. "We don't know how well these devices will perform," he said, and theorists make guesses, but at the nanoscale, unexpected quantum effects can pop up.
Garvey plans to make smaller transistors to see if they can maintain performance. MIT Del Alamo and Antoniadis are also trying to determine the ultimate scaling factor for compound semiconductor transistors, and the duo have made transistors 30 nanometers long. Perfect, and on a tiny scale," Antoniadis said.